The increasing density of MIMO arrays in automotive imaging radars demands highly-parallel systems with low-footprint accelerators, which enable concurrent processing of numerous channels with low-latency. In this paper, we propose ultra-compression schemes for Twiddle Factor ROMs, to reduce the footprint of a variable-length and dual-radix FFT accelerator in a Multi-core DSP for FMCW radars. All schemes are verified with data from a 77-GHz radar, assessed in an FPGA, and implemented in a RISCV-based PE of a Multi-core DSP with an Adaptive Body Bias approach in 22FDX technology for comparing area, leakage, and latency with a dual-ROM equivalent in the state-of-the-art.