In this work, a standard-cell based memory (SCM) compiler is presented to automatically generate a 12T SCM for multiple CMOS technologies operating in near/sub-threshold region. The SCM utilizes Python-MyHDL for RTL and constraints generation. The timing and floor-plan constraints are generated based on user specified technology, memory size, and memory shape inputs. The power, area, energy per access, read delay, and write delays are evaluated for the generated memories of different sizes and shapes.