In this paper, we have proposed a novel design fully reversible-logic based VGGNet architecture in the context of low-power VLSI (Very-Large-Scale-Integration) circuit synthesis. We have implemented two architecture variants of VGGNet, as RL-VGG-16and RL-VGG-19 using only reversible logic gates and circuits. Ideally, no information can be erased during reversible logic operations and therefore, reversible circuits generally dissipate Zero-heat. The proposed architectures have been implemented using VHDL on Altera Arria10 GXFPGA. The comparative analysis demonstrates that proposed RL-VGG-16architecture has achieved an approximately 18.08% decrease in overall power dissipation compared to conventional classical VGG-16 architecture and proposed RL-VGG-19 architecture has achieved an approximately16.48% decrease in overall power dissipation compared to conventional classical VGG-19 architecture approach. Both proposed approaches also have better scalability than classical design approaches.