Due to offset voltage variation, power consumption increases significantly to ensure sufficient performance of flash ADCs. As a solution, statistical selection of comparators based on the order of offset voltages has been proposed. This method achieves at-speed on-chip calibration without the need for analog measurements. To increase the linearity and SNDR under the same power consumption, this paper proposes to use multiple comparator groups with different sizing to tune a distribution of offset voltage. We design and fabricate two ADCs, one with only single comparator group and the other with three comparator groups, in a 65 nm bulk general-purpose process. We confirm the ADC operations at a 1 GS/s and validate order statistic based comparator selection. We then confirm INL improvement by using multiple groups under the same number of total comparators.