This paper proposes a passive switched-capacitor single-ended-to-differential-converter (SDC) as a front-end of a differential SAR ADC to enable digitization of single-ended signals. The proposed solution offers the smallest total capacitance as well as best power efficiency and least chip area. A noise analysis shows that the passive SDC does not result in a noise penalty. A prototype implementation in 65nm CMOS achieves a figure-of-merit of 6.1fJ/conversion-step at 20MS/s, while reaching an SNDR of 54.7dB up to Nyquist and occupying a chip area of only 60um x 36um.