A novel subranging ADC using a Current-Controlled Oscillator (ICO) is presented. A simple low- power technique to reduce the quantization error at each sampling edge is proposed. The idea here is to increase the frequency of the oscillator just before the sampling edge to enhance the oversampling-ratio for a small fraction of the sampling period for subranging. This accomplishes a higher Signal-to-Noise Ratio (SNR) performance without the need for running the ICO at a very high frequency all the time. This ADC is inspired by the strategy used by athletes running marathon where they speed-up close to the finish line to gain more ground against others. The complete system is designed in TSMC 180nm CMOS technology.