Details
Presenter(s)
![Dharmaray Nedalgi Headshot](https://confcats-catavault.s3.amazonaws.com/CATAVault/ieeecass/master/files/styles/cc_user_photo/s3/user-pictures/7354781_0.jpg?h=693f1800&itok=OZLHxutw)
Display Name
Dharmaray Nedalgi
- Affiliation
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AffiliationIntel Technology India Pvt Ltd Bengaluru
- Country
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CountryIndia
Abstract
This paper presents a 2×VDD tolerant I/O buffer with low voltage (VDD) devices. The novel gate tracking circuit and N-well control circuits in mixed voltage I/O buffer is proposed to solve the unwanted leakage paths and dynamic power loss. The proposed design is verified in 22nm FinFET technology. The design can be used for any CMOS technology for 2 × VDD tolerant I/O buffer.