The circuit design and measurement results of a mixed-signal receiver baseband circuit for a wireless high data rate communication system are presented. The circuit design of the two most important system blocks of the sliced receiver baseband architecture, namely the broadband, programmable code-generator circuit, and the integrate and dump correlator circuit are explained. Using parallel sequence spread spectrum (PSSS) with PAM-4 modulated data, a net data rate of 2.22 Gbps is demonstrated with a single receiver baseband slice circuit working with a chip rate of 20 Gcps. A total of 15 slices are required to recover all 15 parallelly transmitted symbols resulting in the net data rate of 33.33 Gbps. This is the first reported implementation of a mixed-signal PSSS baseband circuit.