A CT pipelined ADC profits mostly from a large inter-stage gain (ISG), which is constrained by two major factors: coarse stage quantization noise (QN) and signal leakage. Both have to be minimized to the best possible performance. The coarse stage’s QN can only be reduced by increasing its resolution. The signal leakage can be adjusted in the analog domain by selecting and optimizing a suitable all-pass filter. This paper presents an optimization method and investigates, how an extra low-pass filter can improve performance. Tradeoffs concerning signal leakage, transfer function error and robustness to process deviations are shown.