In this paper, an Electronic Design Automation tool to estimate the vulnerability of digital circuits (META) against transient faults is presented. META analyses both single event transient (SET) and single event multiple transient (SEMT) faults considering the layout of the circuit and the fabrication technology. Unlike simulation based tool, META uses satisfiability modulo theory to calculate soft error rate of the analyzed circuits. The complete analysis flow is automated and our results outperform those obtained by simulation by a average factor of four.