3D integrated circuits are a key technological option that keeps Moore’s Law trajectory beyond conventional scaling. In this class, we learn how machine learning algorithms can solve two important physical design problems for 3D ICs. First, we use unsupervised graph-learning to conduct tier partitioning in 3D ICs. We discuss how graph neural network can extract important features from the given circuit and the underlying 3D IC manufacturing technology specifications to guide tier partitioning for PPA optimization. Second, we learn how machine learning is used to predict wire RC parasitics in the final 3D IC layout before attempting the actual 3D IC physical design. We discuss how such prediction can be done accurately and how this information can be exploited during the subsequent 3D IC physical design for more rigorous PPA optimization.