A low power and high-speed sample-and-hold (S/H) circuit which is suitable for the 16bit pipelined analog-to-digital converter (ADC) is proposed. By using the dynamic bias technique, The OTA in the S/H is realized with lower power dissipation. This S/H is fabricated in 0.18μm mixed signal CMOS process and occupies 0.128mm2. It is integrated in a 16bit 25MS/s pipelined ADC which delivers up to 96.2dB spur-free dynamic range (SFDR) and 75.5dB signal to noise and distortion ratio (SINAD) with 30.1MHz input tone, while the power dissipation is only 34.7mW.