In this paper, we investigate adders and multipliers circuits using Pass Transistor Logic (PTL) and demonstrate its advantages over complementary static CMOS logic in advanced technology nodes. Special focus is put on process, voltage, and temperature (PVT) variations that are disadvantages of PTL. Our investigation shows that PTL-based full adders achieve delay, power, and Power-Delay-Product (PDP) reductions up to 72.9%, 45.7%, and 78.5%, respectively. Further, we demonstrate that our replacement strategy for specific standard adders by PTL adders yields a PDP reduction of 21% for a 8x8 multiplier optimized by a state-of-the-art design flow, among other improvements.