The ramp generator is a crucial circuit component in the design of switching power supply, analog to digital converters, CMOS image sensors, and many other essential circuits. Conventionally, the ramp generator has been implemented with a CMOS comparator that works on the hysteresis principle, which leads to an inherent systemic delay. This paper aims at improving the overall circuit speed by proposing the design of a ramp generator using CMOS proteretic comparator in 180nm TSMC process. It is established from the post-layout simulation that a speedup of 25% is achieved by replacing a hysteretic comparator with a proteretic comparator, and this is done with a trade-off in power consumption and circuit area.