A half-bridge enhancement-mode GaN driver with closed-loop digital calibration is proposed to regulate the VGS ringing to the desired device margin to optimize the slew-rate without compromising reliability. The highside and lowside have independent calibration loops for maximum flexibility, each with 8-bit resolution to cover a wide range of package inductance from 200 pH to 2 nH and GaN devices from as small as EPC2036 to as large as EPC2204. A limited bootstrap driver and a shoot-through guarded negative rail are also included to avoid overvoltage during deadtime periods and false turn-on during Miller plateau periods. This work is designed in a 180-nm BCD process and simulated to verify its functionality under different PVT corners and with different parasitic inductance and EPC GaN transistors. The envelop peak detector, which is the core component that determines the accuracy of ringing regulation, shows a maximum error of 6.2% over PVT corners up to 1 GHz of ringing frequency.