Details
Presenter(s)
Display Name
Chaohan Wang
- Affiliation
-
AffiliationImperial College London
- Country
Abstract
This paper presents an integrated memristive memory (RRAM) capable of storing 4 states in each memory location. In this work, we propose a precise write-in and readout circuit for multi-state memristive memory. The memory is designed over a crossbar array architecture, a 1 transistor 1 memristor (1T1R) topology is employed to eliminate sneak-path currents. Data readout is carried out by two amplifiers and a 12-bit successive approximation analog to digital converter (SAR ADC). The RRAM successfully writes and reads 2-bit information by dividing the resistance of the memristor (memristance) into 4 states.