In this paper, an energy-efficient CycleGAN accelerator is proposed for mobile applications. The numbers of external and internal memory accesses by 98.3% and 68.3% are reduced by spatial data reuse, input feature map reuse, and local data reuse. The computational complexity is reduced 79.4% by zero skip in transposed convolutional layers. An architecture with two processing cores is proposed to improve the utilization by at most 50%. Designed in a 40-nm CMOS technology, the CycleGAN accelerator dissipates 445 mW at 227 MHz from a 0.9-V supply. It achieves 38× throughput-to-area ratio and 127× energy efficiency than a high-end GPU.