The adoption of CAT is increasing for semiconductor companies. CAT is adopted in the context of scan chain tests, and patterns are generated with an ATPG tool. Due to the higher number of patterns generated, an improper CAT-related ATPG flow can lead to a longer test application time. The aim of this paper is to overview different ATPG flows supporting CAT, showing advantages and disadvantages of each approach. Each flow is evaluated in terms of achievable fault coverage and pattern count. The experimental results are presented through a wide range of open-source benchmarks using a proprietary industrial technology library.