The implementation of a power-efficient neuron array system with high throughput and controllable mismatch plays an important role in power-sensitive applications and brain simulations. This paper presents an array of 48 Integrate-and-Fire neurons with axon-sharing architecture implemented in 55-nm CMOS technology. The combination of log-domain circuits and comparator sharing in neuron design achieves the integration of 3125 neurons/mm2 and power consumption of 5.3 pJ/spike. The proposed time modulated axon-sharing synapse architecture realizes 5500 events/s/neuron unit throughput. A novel background calibration module is integrated to reduce the mismatch between neurons. Simulations present a 51.7% improvement in the CV of interspike interval. Finally, we validate the architecture by implementing a spiking neural network for solving a 3-stage Sudoku Puzzle. 100% success rate is obtained after calibration.