A graph representation is proposed to model analog circuits at the transistor level. Edge-conditioned convolution (ECC) is utilized, where weight matrices conditioned on the edge attributes are trained in a local neighborhood of a given node. A relational graph is constructed to model groupings of devices for each level of the hierarchy provided by a designer. Each adjacency matrix of the relational graph is processed by a graph isomorphism network (GIN) layer to update the node embeddings, described as a Circuit-GIN layer. Circuit-GNN is trained on data from four op-amp topologies to predict four performance parameters. Results indicate that the ECC-based models outperform a GCN-based model in the prediction of all of the performance parameters, which results from the additional edge information learned by the ECC layer. The Circuit-GNN outperforms the ECC-only model by up to 16.7% in R2 scores. The work validates the expressive power of the proposed GNN model to generate embeddings that distinguish between different circuit graphs. The generalization of GNNs renders feasible the simultaneous learning from different analog topologies.