Standard delay cells (SDCs) are commonly used for timing synchronization in digital designs. Due to the skewed tran-sistor sizing, the SETs induced in SDCs may be stretched during propagation through the cell, thus increasing the probability of soft error rate. In this work, a simulation analysis of the SET effects in 130 nm SDCs is presented. The results have shown that the induced SETs may be up to 1.46 ns wide, which is more than 800 ps longer than the SET in standard combinational cells under the same simulation conditions. As the conventional gate-level SET mitigation techniques are not effective against long SETs, we have investigated two hardening solutions for SDCs: (i) complete duplication with a guard gate, and (ii) partial duplication with a guard gate applied to the most sensitive inverters in the SDC. Both solutions can reduce significantly the generated SET pulse width with the delay overhead of less than 250 ps. The estimated area overhead per cell is around 115 % for complete duplication and 80 % for partial duplication.