This paper provide a comparative study of design techniques for bootstrapping in the sample-and-hold of energy-efficient successive approximation register analog-to-digital converters (SAR ADCs). The need for bootstrapping is investigated. It is followed with an in-depth examination of the design, advantages, and disadvantages of bootstrapped switches. Design considerations in choosing bootstrapping capacitors and negative-gating capacitor in low-leakage bootstrapped switches are investigated. The nonlinearity and power consumption of bootstrapped switches are compared and the impact of supply voltage reduction on the nonlinearity and power consumption of bootstrapped switches is investigated utilizing TSMC 130 nm 1.2 V CMOS technology.