Power net routing in analog design determines wire width and routing path such that routing area is minimized and IR-drop constraints imposed on the blocks are all satisfied. We propose two-stage routing, consisting of trial- and main-routing. In trial routing, RL is applied to find the routing path and wire width assuming bigger routing grids. In main routing, we take each net one-by-one and apply ILP to determine exact path along smaller grids, while the result from trial routing is respected. Experiments indicate that the proposed method yields on average of 12% smaller routing area compared to the state-of-the-art.