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Video s3
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    Author(s)
    Display Name
    Xiaoyuan Wu
    Affiliation
    Affiliation
    East China Normal University
    Display Name
    Yao Xiao
    Affiliation
    Affiliation
    East China Normal University
    Display Name
    Zitong Zhang
    Affiliation
    Affiliation
    East China Normal University
    Display Name
    Leilei Huang
    Affiliation
    Affiliation
    East China Normal University
    Display Name
    Boxiao Liu
    Affiliation
    Affiliation
    East China Normal University
    Display Name
    Chunqi Shi
    Affiliation
    Affiliation
    East China Normal University
    Display Name
    Jinghong Chen
    Affiliation
    Affiliation
    University of Houston
    Display Name
    Runxi Zhang
    Affiliation
    Affiliation
    East China Normal University
    Abstract

    This paper proposes a high-efficiency low-ripple dual-mode switched-capacitor (SC) DC-DC converter for lowpower IoT and wearable device applications. A hybrid selfbiased current scheme (HSBC) is developed to achieve low output voltage ripple and fast response. Two supply voltage domains of HSBC and clock drive controller circuit are introduced to reduce the power loss of the control circuit. An on-chip ultra-low-power bias circuit is also designed to minimize the power loss of the bias generator. The proposed DC-DC converter is implemented in a 40 nm CMOS process. Post-layout simulation results show that the converter realizes 1.6-1.8 V to 0.4 V conversion. The peak efficiency is up to 88% at 5 uA, and the voltage ripple is less than 10 mV over a load range of 10 nA-10 uA. The response time of the converter is less than 15 us.