A tunable 10-stage all-pole (Papoulis) low-pass filter occupying 0.1815mm2 is designed and integrated as a building block in a 22nm CMOS FDSOI receiver for the 5G. Each filter stage comprises of a two-stage unity gain buffer with common mode feedback loop. Tunable resistors between each stage determine the bandwidth of the filter in the range of 0.7 GHz to 1.5 GHz. An identical filter structure, but with the outputs fed back to the inputs functions as an oscillator. Correlating the oscillation frequency with the filter bandwidth, under the same tuning conditions, the filter bandwidth can be calibrated to account for PVT variations. Measurement results show an in-band OIP3 of 8.8dBm and a nearly linear phase response at a power consumption of 35mW to 50mW from a 1V supply. The power/pole of 3.3mW/GHz is the best when compared to other filters from literature.