Details
Poster
Presenter(s)
Display Name
Ghita Harcha
- Affiliation
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AffiliationUnversité Bretagne Sud
- Country
Abstract
In this paper, we present a lightweight secured AES hardware implementation designed to further resist to Side Channel Attacks relying on Power Analysis. The proposed architecture is based on an 8-bit data-path, and the protection is provided by shuffling computations and memory locations. Our shuffling module is based on a permutation network controlled by a Random Number Generator and leads to the best compromise between security, area, and performances compared to state-of-the-art.