In this paper a simplified hardware implementation of a dot product arithmetic operation with constant coefficients is presented. The proposed methodology exploits a combination of distributed arithmetic and common sub expression techniques. An algorithm is introduced for identifying the common sub partial sums systematically. Subsequently, a hardware architecture is proposed and the proposed circuits are synthesized in a 90-nm 1.0~V~CMOS standard-cell library using Synopsys Design Compiler. Comparisons reveal significant reduction of 52\% and 23\% in area and power respectively for 1.5~ns delay over a regular dot product constant multiplier.