A PUF based hardware security circuit (PBHSC) is proposed for testable ICs containing design for testability (DFT) circuitry. DFT techniques such as scan chain enhance the controllability and observability of internal nodes of an IC, which leads to vulnerabilities such as IP theft or tampering. The proposed solution restricts unauthorized access to DFT structures by inhibiting enable pin of test circuitry. A PUF based lock and key mechanism enable test circuitry only upon successful authentication of the user. Area and power consumption overheads and the latency of the proposed technique are insignificant as these are independent of the size of the circuit under test (CUT). The proposed technique is compatible with the industry-standard DFT architectures such as scan-chain, BIST, JTAG, etc. The proposed design is implemented on Zynq UltraScale+ ZCU102 FPGA and Vivado design suite. PBHSC consumes 11 LUTs, 7 registers, 1 clock cycle to produce output, and 18mW power at 100MHz.