Details
Presenter(s)
![Keisuke Sakamoto Headshot](https://confcats-catavault.s3.amazonaws.com/CATAVault/ieeecass/master/files/styles/cc_user_photo/s3/user-pictures/91001.jpg?h=2c4e73f8&itok=dKWr7-ga)
Display Name
Keisuke Sakamoto
- Affiliation
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AffiliationTohoku University
- Country
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CountryJapan
Abstract
We describe an MTJ (magnetic tunnel junction)-based nonvolatile CPU based on RISC-V that is an open-source and highly flexible instruction set architecture. This CPU with an accelerator can efficiently perform intermittent operations by incorporating its control as one of the custom instructions in the instruction set, which is suitable for energy-efficient IoT (internet-of-things) applications. Through the performance evaluation of the CPU in a 55-nm CMOS/MTJ-hybrid process technology, we show that our CPU can save up to 58% of energy consumption compared to that of conventional approaches with the same CPU and accelerator.