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Video s3
    Details
    Presenter(s)
    Keisuke Sakamoto Headshot
    Display Name
    Keisuke Sakamoto
    Affiliation
    Affiliation
    Tohoku University
    Country
    Country
    Japan
    Author(s)
    Display Name
    Keisuke Sakamoto
    Affiliation
    Affiliation
    Tohoku University
    Display Name
    Masanori Natsui
    Affiliation
    Affiliation
    Tohoku University
    Display Name
    Takahiro Hanyu
    Affiliation
    Affiliation
    Tohoku University
    Abstract

    We describe an MTJ (magnetic tunnel junction)-based nonvolatile CPU based on RISC-V that is an open-source and highly flexible instruction set architecture. This CPU with an accelerator can efficiently perform intermittent operations by incorporating its control as one of the custom instructions in the instruction set, which is suitable for energy-efficient IoT (internet-of-things) applications. Through the performance evaluation of the CPU in a 55-nm CMOS/MTJ-hybrid process technology, we show that our CPU can save up to 58% of energy consumption compared to that of conventional approaches with the same CPU and accelerator.

    Slides
    • [SHORT] Energy-Efficient Nonvolatile RISC-V CPU with a Custom Instruction-Controlled Accelerator (application/pdf)