The main contribution of the proposed work is to address the direct-down-conversion and impedance matching problem of sub-sampling receiver architecture. A scheme for direct down-conversion and impedance matching at RF port of the mixer using the third harmonic of sampling frequency is proposed. Hence, the proposed receiver architecture requires low power clock generation circuit than RF sampling receivers. An example architecture is simulated, and it is observed that the performance predicted by analytical equations is in agreement with post-layout SpectreRF simulations. The proposed architecture achieves NF of 8.6dB, conversion gain of 21dB, IIP3 of -1dBm, and 50Ω input impedance matching.