This paper reports a robust methodology to design high accuracy and low noise multiphase clock generators based on Self-Timed Ring Oscillators (STRO). An algorithm generating from an STRO any number of Overlapping or Non-Overlapping phases is described. A VHDL package integrating the analog behavior of the STRO has been written to evaluate and simulate the proposed algorithms. In order to demonstrate the effectiveness of this algorithm, these clock generators have been designed in 28 nm FDSOI technology. The simulations show compatibility between the digital simulations and the transistor level simulations.