Approximate Computing has found significant use in error-tolerant applications. This is exploited to design hardware aimed at reducing delay, area and power. We propose a Segmentation based Approximate Multiplier(SAM) to multiply two unsigned binary numbers. The proposed design reduces the Partial Products Matrix in the order of n×(2n−1) to the Reduced Partial Product Matrix of the order 4×2n. μ-SAM, an optimized version of SAM further minimizes the area and power consumption of SAM. The basic design consumes 32.43% lesser area when compared to Wallace Tree Multiplier and produces results that are 89.1% more accurate than the existing state-of-the-art designs.