The high adoption rate of deep learning has set new demands on computational throughput, latency, and power efficiency of the computing infrastructure. Hence, there is renewed interest in high-frequency analog circuits for deep learning inference. This paper presents early work on the design of an analog CMOS accelerator that performs CNN inference in parallel and in real-time. The accelerator was designed in a 45 nm CMOS process and simulated in Cadence Spectre. The proposed solution also employs Xilinx RF System-on-Chip (SoC) devices to interface digital inputs and outputs with the proposed RF-rate inference accelerator.