In this paper, we proposed a resource-efficient ‘QRS’ detector with superior detection accuracy. Inspired by the strategy of the folded architecture, we adopted a reconfigurable time-sharing computation unit with a pipeline schedule. To further precisely locate the position of the ‘R’ peak and minimize the extra hardware cost, we designed the position calibration unit(PCU) based on the data compression technique. The proposed architecture was implemented on Xilinx Zynq-7000 with Verilog programming language. The proposed architecture achieves a sensitivity Se of 99.76%, a precision+P of 99.85%, and a detection error rate DER of 0.40% on the MIT-BIH database, which attains the best performance compared to state-of-the-art designs. Furthermore, the proposed architecture achieves better hardware efficiency with 13×, 1.28×, and 4.35× reduction in computing resources, storage memory, and power consumption, respectively.