This paper presents a correlation-based 3rd-order inter-stage gain error background calibration technique for high-performance pipeline ADCs, with the reduced signal swing overhead to only 8% during the pseudo noise (PN) sequence injection. This is achieved by exploiting the use of paired comparators along with a dedicated calibration algorithm, namely the adaptive dither injection calibration (ADIC) technique, which further alleviates the trade-off between the signal-to-noise ratio and the non-linearity. Monte Carlo simulation results of a 16-bit 100MS/s ADC show that with an amplifier of 20dB loop gain, the spurious-free dynamic range (SFDR) is improved from 64.8dB to a mean value of 106.6dB and a standard deviation of 1.1dB.