This paper presents a fast and an efficient digital LDO (DLDO) regulator utilizing a clock-less ratioed logic comparator (RLC). In addition to eliminating the clock, the proposed RLC-DLDO removes the shift registers used in the conventional DLDO. It achieves a transient speed improvement in the ns range and a quiescent current reduction by 9X over the conventional design that targets uA load current. The design is implemented in 22nm FDSOI and occupies an active area of 0.0171mm^2. The simulation results show that the peak efficiency is 99.9% and the load transient response time is 5ns at VL=0.5V.