For an extensive power system network, solving the power-flow problem becomes computationally very burdensome. For a massive power grid, large memory consumption and calculation steps are required to find the solution which puts more constraint on the available resources for the processor-based digital solver. This paper shows the feasibility of using a Phase Locked-loop (PLL) based novel architecture for a mixed-signal emulator by presenting the emulation data for 14 bus system which reaches steady state after 15 µs with 3 order of computational speed improvement.