Deploying ASICs at the tip of the catheter is challenging, as power is delivered through a long and thin wire, limiting the power integrity. Also, since the catheter needs to fit into the diameter of a blood vessel or other narrow channel in the human body, there is no room for bulky decoupling capacitors. Finally, power consumption must be optimized, as the energy density may lead to prohibitive heating of tissues and fluids. Still, while targeting better performance the requirements for bandwidth and accuracy consistently increase, ultimately demanding precise on-chip clock generation for digitization. In this paper we propose a circuit for at-the-tip clock generation in smart catheters, comprising a low-drop out regulator, voltage and current references and a low-jitter digitally controlled oscillator. The LDO achieves a full-spectrum PSRR of 50dB with an output load of 10mA. The DCO, supplied by the aforementioned LDO, achieves a phase noise of -104.5dBc/Hz at 1MHz offset and oscillating at 1.25GHz. The proposed clock generator allows digitization at 200MSps with a maximum SNR of 56.3dB for an input signal of 50MHz if phase noise is integrated from 100kHz to 625MHz.