This paper presents a low-power and area-efficient finite field multiplier based on irreducible all-one polynomials (AOP). The proposed architecture implements the AOP multiplication algorithm in three stages, which are reduction network, AND network (multiplication), and three input XOR tree (accumulation), while state-of-the-art implementations distribute reduction, multiplication and accumulation operations in a systolic array. The optimization reduces the overall number of sequential instances and provides lower pipeline latency compared to literature. This leads to the reduction of power dissipation and area for a targeted system clock frequency.