Details
Poster
Presenter(s)
![Lantao Wang Headshot](https://confcats-catavault.s3.amazonaws.com/CATAVault/ieeecass/master/files/styles/cc_user_photo/s3/user-pictures/80711.jpg?h=52be58f6&itok=BJ-614Oz)
Display Name
Lantao Wang
- Affiliation
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AffiliationRWTH Aachen University
- Country
Abstract
This paper presents a low-dropout regulator (LDO) with the capability to provide a stable 0.9 V supply voltage for fluctuation-sensitive circuits such as the voltage-controller oscillator in a frequency synthesizer. The LDO uses a low noise architecture that separates two feed-back loops with a low-pass filter with a extremely low 3-dB frequency of 8.15 Hz. The circuit is designed in a 28-nm technology, operating with a 1.8 V external voltage and able to supply maximum current of 25 mA. Analysis and implementation for optimizing power supply rejection ratio (PSRR) of the circuit are also addressed in this paper.