This paper proposes low power optimization using swarm intelligence algorithm for 2 scenarios- transistor sizing based PVT aware static power reduction for conventional de- signs and low power standard cell generation for approximate computing. In both the scenarios, we explore a lower abstraction level and see how standard cells can be tuned to a power-delay- quality optimal point. For conventional design transistor sizing, fabrication process parameter variations (for ±3σ design) in addition to a wide range of temperature (-55 o C to 125 o C) and supply voltage (±10%) variations have been incorporated to obtain robust sizing solutions. The approach has been applied on numerous single and multi-stage circuits (including ISCAS benchmarks) while proposing a dual sizing solution for non-critical and critical path cells. For approximate systems, we present algorithm generated full adder designs for speech processing systems. The designs vary in terms of accuracy and power. Results show leakage reductions up to 58.2% for conventional and 66.8% for approximate designs for 22nm metal gate high-K (MGK) technology cells.