This paper presents a Track and Hold sampling buffer topology, which allows sampling the signal inside the buffer itself while achieving very high linearity. The circuit operations and its large-signal behavior is analyzed and the key design strategies to maximize linearity are discussed. Then, a 60 GS/s, 52.6 dB SFDR, 8 ways interleaved simulated prototype in TSMC 5 nm technology, consuming 2.52 mW from a 0.9 V supply, is compared to the state-of-the-art sampling buffers, showing linearity improvement.