Machine to machine communication (MMC) technologies are becoming more in need in the current age of connected devices. Narrow Band Internet of Things (NB-IOT) is one of the established and popular MMC technologies. Power consumption reduction is one of the main aims of NB-IOT specification.In this paper, hardware acceleration of a fully parallel viterbi decoder architecture for NB-IOT is implemented. Profiling of the NB-IOT physical layer down-link chain on Zync-7000 SoC is investigated. As a result, the Viterbi decoder was identified as the most power consuming component. Finally, Hardware acceleration of a repetitive pattern based fully parallel Viterbi decoder is proposed and implemented. With the use of Virtex-7 Field Programmable Gate Array (FPGA), Gbps throughput is achieved.