Details
Poster
Presenter(s)
![Chaiyanut Aueamnuay Headshot](https://confcats-catavault.s3.amazonaws.com/CATAVault/ieeecass/master/files/styles/cc_user_photo/s3/user-pictures/17941_0.jpg?h=2c4e73f8&itok=wtv6m2Oe)
Display Name
Chaiyanut Aueamnuay
- Affiliation
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AffiliationOregon State University
- Country
Abstract
The gm/ID-based design of analog ICs introduced by Silveira, et al. employs a transistor sizing methodology using SPICE-generated lookup tables. In the design of ultra-low-power amplifiers, the iconic plots of gm/ID vs VOV suggest that some devices should be operated deep in weak inversion where gm/ID is near maximum. Performance parameters such as gain, bandwidth, thermal noise, power dissipation, etc., benefit from this choice. However, in applications where small-signal settling time is critical, the unity-gain phase margin is a parameter of paramount importance. PM (i.e., small-signal settling time) vs. VOV (i.e., strong, moderate or weak inversion) design considerations are presented.