FinFET based, low swing clocking with rotary traveling wave oscillators (RTWO) is presented in this paper. It is shown that the low-swing clock signal generation by RTWOs is an ideal fit, thanks to FinFETs accommodating high frequency operation and voltage scaling better than planar CMOS transistors. Low swing clocks are aimed at lowering the power dissipation of the clock networks, while maintaining the full voltage operation of non-clock components (such as logic and memory). This work shows that robust low swing (LS) RTWOs can be designed and implemented on-chip with FinFET based technologies. To this end, SPICE simulations are performed on the ISPD’10 clock benchmark circuits operating at 2.25GHz and 3GHz in the 16nm FinFET technology node. LS–RTWO based designs are compared to ADPLL based designs operating at the same target frequency. At 3GHz, the LS–RTWO consume 36% lower power with 42.7 dB better phase noise @10MHz on comparison to ADPLL based designs.