This paper presents a study comparing complex gates that use Series-Parallel and Non-Series-Parallel associations, including the time-zero variability and the BTI impact. A comparison of 53 logical functions was performed, showing that the reduction in the number of transistors and area of NSP structures does not assure better power and timing results, with the SP structure gates presenting a smaller power. Structures built where both the pull-up and pull-down networks are optimized individually presented better results in average value and robustness to variability and aging.