Spintronics presents great promise for efficient processing and storage of information in the post-Moore era, thanks to its attributes of non-volatility, excellent integration-density, near-unlimited endurance and compatibility with CMOS process-technology. Today’s state-of-the-art EDA tools primarily use AND-Inverter Graphs (AIGs), Majority-Inverter Graphs (MIGs) and XOR-Majority Graphs (XMGs) for representing any complex Boolean logic. This paper demonstrates how the XMGs synthesized by EDA flows can be more-efficiently mapped to spintronic fabric using a novel domain wall motion-based XOR device. We develop a device-to-system simulation-framework to precisely evaluate the post-mapping (to domain-wall gates) performances of synthesized networks. Our study over several challenging benchmark-suites shows that the use of this XOR-gate enables the efficient mapping of XMGs while improving the {size, depth, size.depth, energy, EDP} performances of the network by averages of {31.54%, 19.00%, 41.56%, 38.03%, 45.47%} over those of mapped MIGs.