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![Jinkai Wang Headshot](https://confcats-catavault.s3.amazonaws.com/CATAVault/ieeecass/master/files/styles/cc_user_photo/s3/user-pictures/17421.jpg?h=3575139a&itok=Re-TDiU_)
- Affiliation
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AffiliationBeihang University
- Country
In-memory computing is highly promising to address the processor-memory data transfer bottleneck in current computational paradigm. We firstly propose a time-domain in-memory computing (TIMC) scheme based on high-speed low-power toggle spin torque random access memory (TST-MRAM). The difference of voltage drops of bitline caused by simultaneously-activated bit-cells is reflected to time domain. Reconfigurable logic operations can be performed by utilizing D flip-flops (DFFs) to record the outputs at different moments. In order to demonstrate the advantage of this scheme in terms of speed and energy consumption, an efficient multi-digit addition circuit has been designed and analyzed. Compared with existing IMC scheme, such as spin-transfer torque computing-in-memory (STT-CiM) structure, up to 67% energy saving and 10 times delay improvement can be achieved in the case of four-digit addition by using TIMC scheme.