We propose an accurate and computationally efficient Gradient Boosting approach for the estimation of statistical aware leakage power and propagation delay in the state of art CMOS/FinFET standard digital cells. The proposed model estimates the leakage power and propagation delay w.r.t variations in process, temperature and supply voltage. The distinguishing feature of the proposed approach is its compatibility with both CMOS and FinFET technologies. Moreover, the performance of the proposed model is consistent with different technology nodes. Exhaustive tests report an average error of <1% in 16nm CMOS and FinFET nanoscale standard digital cells w.r.t analog HSPICE simulations with a speed-up advantage of several orders. Further, the complex cell estimation can be carried out through pre-characterized standard cells abstaining longer simulations.