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![Ramin Rajaei Headshot](https://confcats-catavault.s3.amazonaws.com/CATAVault/ieeecass/master/files/styles/cc_user_photo/s3/user-pictures/18171.jpg?h=f35c3bdd&itok=UAURWzsD)
- Affiliation
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AffiliationUniversity of Notre Dame
- Country
The emerging negative capacitance FinFET (NC-FinFET) device is a promising technology for the design of low-power VLSI circuits. This paper proposes ultra-low-power, high-performance, and low-area dynamic random access memory and sequential logic circuits based on NC-FinFETs. These circuits leverage the fact that NC-FinFETs have low leakage currents which help to facilitate a dynamic storage (DS)-based logic design style. This can in turn lead to reduced area overhead and help to compensate for higher delays that may be associated with NC-FinFETs. Our proposed circuit-level solutions can improve the data retention time of DS latch, flip-flop, and eDRAM circuits. Simulations with 14nm baseline FinFET (BS-FinFET) and NC-FinFET device models reveal that the proposed circuits offer up to 83.5% improvement in area-power-delay-product when compared to conventional BS-FinFET static-storage counterparts.